BENGALURU · FULLTIME
Design Engineer
Delancey Technologies
Bengaluru · onsite · Posted 68d ago
Sourced from
Undisclosed5–10 yrsfulltimeBengaluru
About a minute. You'll make an account on the way through.
agent · working
- Read this posting0.2s
- Found the form on Naukri · 6 questions to answer1.4s
- Decided the answers for all of them2.1s
- Tailor your résumé to this role
- Waiting for you
Section · 01
About this role
- 2+ years of experience in the field of front-end design, synthesis and STA
- In-depth knowledge of synthesis, static timing analysis and constraints development
- In-depth knowledge of RTL design fundamentals
- In-depth knowledge of Verilog and System-Verilog
- In-depth knowledge of front-end tools (Verilog compilers/simulators, linters, clock-domain crossing checkers, RTL synthesis, STA)
- DFT knowledge is a plus
- Good knowledge of scripting languages such as Perl, Tcl and Python
- Strong communication and presentation skills
-
- Experience on DFT logic insertion using Mentor Tessent or SNPS Testmax Hierarchical flow.
- Experience on DFT logic verification and ATPG
-
- Experience on Top-Level Block-Level DFT verification covering Mbist , tap , BSD, Stuck at fault , transition fault. In both Zero delay and with timing
- Experience on DFT logic insertion using Mentor Tessent Hierarchical flow.
Disclaimer: This job posting & Location has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Sourced from naukri
Section · 02
Skills
Static Timing AnalysisAtpgMentorPerlVerilogSystem VerilogDFTPythonFront End DesignFront End