Design Engineer II
Cadence · Noida · onsite · Posted 19d ago
Not disclosedFresherfulltimeSourced from
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About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Role Overview:
Key Responsibilities:
- Verification Infrastructure:Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
- Advanced Verification:Champion the integration of formal verification, and AI-driven coverage analysis.
- Cross-Functional Collaboration:Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.
Required Qualifications:
- B.Tech/M.Tech in ECE with
- Experience inSystemVerilog/UVMandC/C++for architectural modeling.
- Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
- Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
- Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.
We're doing work that matters. Help us solve what others can't.
Sourced from foundit
Skills
tclcPerlUVMSystem VerilogPCIEARMRISC-VambaPython
About Cadence
Cadence
San Jose
CR
About
Cadence is a pivotal leader in electronics and system design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world??s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For
Industries
AerospaceArtificial Intelligence (AI)BiopharmaElectronic Design Automation (EDA)HardwareMobile