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    Job · 15953610

    CDS Infra Projects logo

    Design Engineer II

    CDS Infra Projects · Bengaluru · onsite · Posted 46d ago

    Not disclosed2–10 yrsfulltimeSourced fromFoundit

    About a minute. You'll make an account on the way through.

    About this role

    At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

    The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence.

    Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.

    Minimum Qualifications & Professional Experience

    • 2-10years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
    • 5-7 years of management experience leading/mentoring a small team of engineers
    • Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
    • Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
    • Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard's specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon.
    • Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize.
    • Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements.
    • Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus.
    • Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures.
    • Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification
    • Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++

    We're doing work that matters. Help us solve what others can't.

    Sourced from foundit

    Skills

    Ethernet PCIe UCIe standards and ProtocolsPhysical Layer and Protocol layer experiencecFPGAC plus plusoscilloscopesAnalyzersDebug skillsProtocol ExercisersBit Error Rate TestersVerilog RTL codingPythonElectrical and Protocol Interoperability and Compliance test suitesESD Latchup HTOL tests

    About CDS Infra Projects

    CDS Infra Projects logo

    CDS Infra Projects

    Engineering & Construction

    Gurgaon / Gurugram, Haryana

    India

    ₹8.3L PA avg

    Avg at CDS Infra Projects

    About

    Cadence is a pivotal leader in electronics and system design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world?????s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For

    Industries

    Software Product

    Employee ratings

    10 reviews

    3.3/ 5

    Culture

    3.2

    Career growth

    2.7

    Work-life

    3.4

    Employees rate it well for

    Work-Life Balance33Work Satisfaction33

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    Design Engineer II · waiting for your command