Design Engineer I ( Synthesis/LEC/CLP )

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

Location: Bangalore / Pune

Experience: 0-2 Years

BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

We are looking for a Design Engineer to join our synthesis/LEC/CLP team, supporting execution-level tasks across the ASIC design flow. This is a strong opportunity for an engineer early in their career to build deep expertise in synthesis, Logical equivalence checking and low-power design.

• Assist in running and monitoring Logical Equivalence Checking (LEC), Logic Synthesis, and Conformal Low Power jobs across design blocks
• Support constraint reviews, generation, and basic debug
• Help track and document LEC synthesis status across blocks.
• Learn and apply power intent basics to support CLP sign-off tasks
• Support ECO script writing and basic scripting tasks (Tcl/Perl/Python)
• Maintain clean documentation of runs, issues, and findings.

• 0-2 years of experience: internship or academic project experience with ASIC flows is a plus
• Bachelors/master s degree in Electronics, Electrical Engineering
• Basic understanding of the complete ASIC design flow.
• Basic scripting skills (Python, Perl, Tcl, or Unix shell)
• Strong analytical and problem-solving skills; eager to learn EDA tool flows
• Good communication skills and ability to work well in a team

• Exposure to Cadence tools (Genus, Conformal) through coursework or internship
• Basic understanding of digital logic design and computer architecture

Regards

K Madhu Prasad

kmadhup@cadence. com