Design Architect

Cadence HSV groupisresponsible fordevelopment of the Palladium and Protiumemulation hardware and softwaresystem. This includesdevelopingdesign andverification components for complex protocols, to be used for emulation, for e.g.SystemVerilog/Verilog components and SW components written in C/C++ and SV-UVM. It also requires development of system level RTLmethodologies forstitchingtogetherlarge complex RTL designs in a scalable andreusablemanner usingand developing advanced tools including those that use AI and ML techniques.

A critical elementwith building these SoC modelsis performance,encompassingperformance of the AVIP, the underlying hardware-software design/integration, thecompiler and theprocessor-basedPalladium emulator hardware system.

Job Description:

We are seeking a skilled HW and/orDesign EngineeringArchitecttoleadbuildingrepresentative SoCsub-systemsusing partner systems(ARM, others)and Cadence designand verificationcollateral.The main task isto build ARM CSS based systemsusing Cadence AVIPS andIP, portthese toPalladium/Protium hardware and softwareandensure functional correctness andmake recommendations forperformanceimprovements.Experience with SoC design, verification, ARM bus protocolsand performance analysis isrequired.Familiarity with or interest in developing new methodologies for SoC Integration and Verification Automation is a plus.

Skills needed:

• 15-18years of hands-on HWRTLdevelopmentand verificationexperience

• Emulation experience on Palladium/Protium

• Expertisein AMBA and CHI protocols

• Knowledge with design/integrationof SoCsystems

• Experience with performance analysis of complex hardware-software systems.

• Familiarity with standard communication protocolsPCIe, CXLis a plus

• Good communication skills, excellent inter-personal skills, motivated individual

• Ability to analyze and propose solutions to complex problems.