Design and Verification Engineer

Role & responsibilities

• Understand design specifications and develop comprehensive verification plans.
• Develop and maintain SystemVerilog/UVM-based testbenches.
• Create test scenarios, sequences, drivers, monitors, and scoreboards.
• Develop directed and constrained-random test cases.
• Perform functional and code coverage analysis.
• Debug simulation failures and identify design issues.
• Verify IP-level and SoC-level functionality.
• Work closely with RTL Design and other verification teams.
• Track bugs, document results, and support verification sign-off.
• Participate in regression testing and coverage closure.