Design and Verification Engineer

Job Title:[SoC Verification Engineer]

Company: MetaVLSI Technologies

Location: Bangalore

Experience: [4-12 Years]

Note:[Work from Office]

Preferred: [Immediate Candidate

Job Description

• Experience level: 4 to 12 years Independent Verification Ownership of IP DV.
• Collaborating with various cross functional teams at multiple geo locations as part of execution.
• Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts)

Role and Responsibilities:

• Domain: AXI, PCIe, UCIe protocol experience is highly preferred
• Must have experience in developing test benches for IP/Subsystems/SoC.
• In depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV.
• Previous experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities.
• Strong hands on experience with common verification tools and methodology including UVM/ System Verilog/CDV/MDV, DV signoffs.
• Must have a strong domain expertise in one or more following areas - AXI/PCIe/UCIe.
• Experience in Hybrid test benches (SV, SystemC, Python) and SystemC based reference model test vectors/stimulus based verification is desirable.