Design and Verification Engineer
Leadic Design · Bengaluru · hybrid · Posted 25d ago
Undisclosed2–7 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
DV Engineer with 3+ years’ experience in SystemVerilog/UVM and high-speed protocol verification. Hands-on with PCIe, USB, Ethernet, MIPI or CXL. Strong in testbench development, coverage, assertions and debug.
Perks and benefits
Competitive salary, global client exposure & growtSourced from naukri
Skills
DdrUSBEthernetPCIESOC VerificationDesign VerificationUCIepcie gen3