Design and Verification Engineer
Soc Bridge · Hyderabad · onsite · Posted 27d ago
Undisclosed4–9 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Role & responsibilities Design Verification Engineer
Preferred candidate profile
Must have strong knowledge on SV,UVM. Worked on DDR and PCIE will be added benefits.
Sourced from naukri
Skills
VerilogUVMDesign Verification