Design and Verification Engineer

Core Requirements
Basic understanding of CMOS and gate level circuit designs
Familiarity with SPICE
Familiarity with Verilog simulations
Good communication skills and ability to work well in a team

Preferred Qualities
Analytical capability for complex gate level circuit designs
Experience in SystemVerilog, PLI coding
Experience in UVM Test Bench
Experience in DRAM, SRAM or other memory related fields
Experience in AMS verification and co-sim
Experience Level 5+ years