HYDERABAD · FULLTIME
Design and Verification Engineer
Leadic Design
Hyderabad · hybrid · Posted 1d ago
Sourced from
Undisclosed4–9 yrsfulltimeHyderabad
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Section · 01
About this role
Hiring PCIe & GLS Verification Engineers with 4+ years of experience in SystemVerilog/UVM. Experience in PCIe Gen5, GLS, RTL verification, assertions, coverage, debugging, and protocol verification preferred.
Sourced from naukri · view original
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Section · 02
Skills
GLS VerificationUVMSystem VerilogSOC VerificationDesign VerificationGLSPCIe Gen5