Design and Verification Engineer

Role & responsibilities

Required Skills:
*) Strong experience in SystemVerilog and UVM methodology
Hands-on expertise in high-speed interface protocols (PCIe / USB / DDR / Ethernet / AXI, etc.)
*) Good understanding of verification concepts, coverage, assertions, and debugging
*) Experience with simulation tools (VCS, Questa, Xcelium, etc.)
*) Strong analytical & problem-solving skills

Preferred candidate profile

48 years of experience in ASIC/SoC Functional Verification.
Strong hands-on experience in System Verilog and UVM.
Experience with high-speed protocols such as PCIe, USB, DDR, Ethernet, AXI/AMBA.
Good understanding of testbench development, assertions, functional coverage, debugging, and verification methodologies.
Hands-on experience with VCS, Questa, or Xcelium.
Strong analytical, debugging, and problem-solving skills.
Candidates with experience in IP/SoC-level verification will be preferred.