Design and Verification Engineer
Leadic Design · Bengaluru · hybrid · Posted 63d ago
Undisclosed4–9 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
DV Engineer with strong SystemVerilog and UVM skills. Experience in testbench development, constrained-random testing, functional coverage, assertions, regression, and RTL debug.
Sourced from naukri
Skills
DdrUSBSVEthernetVerilogUVMPCIESOC VerificationDesign Verification