CPU Verification Engineer - Core Enablement

Silicon Design Engineer 2

The Role

AMD is looking for talented, detail-oriented, and motivated design verification engineers who are interested in functional verification of x86 microprocessor cores. You ll have the unique opportunity to work on and learn about some of the industry s cutting edge micro-architectural designs while you create verification models and plans for verifying the architecture of the X86 CPU core. Your contributions will impact products that span the global x86 market from server to desktop and laptop designs.

The Person

The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization, and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design or verification issue. You should be adaptive, self-motivated, able to strike a balance between collaborative problem-solving and independent solution development. Candidate should have a solid track record of working on complex designs with hands-on experience on architecting and developing test-bench, test-bench components, test-planning and execution of test plan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones.

Key Responsibilities

• Collaborate with architects, design engineers, and other verification engineers to understand new CPU features to be verified.
• Build test plan documentation, accounting for interactions with other features, various design sub-units within CPU, SOC and also hardware, firmware, and software use cases if applicable.
• Estimate time required to write new feature tests and any required changes to the test environment and tools.
• Develop directed and random verification tests.
• Understanding the existing test bench setup and look for opportunities to improve it.
• Debug test failures to determine the root cause; work with RTL design engineers to resolve design defects and correct any stimulus or testbench issues.
• Use scripting and internal AI tools to come up with innovative solutions to day-to-day problems and to improve individual as well as teams productivity.
• Develop functional coverage properties as needed.
• Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements.
• Mentor junior engineers as needed.

Preferred Experience

• ASIC design verification experience of 5 to 10 years.
• Understanding or technical expertise in functional verification of microprocessor designs.
• Experience with Verilog/System Verilog HDL, programming in Perl/Python/Ruby, C/C++, Makefile and logic simulation.
• Experience with x86, ARM or any other industry standard microprocessor architecture.
• Strong understanding of computer architecture and assembly programming, preferably x86.
• A passion for computer architecture and a good understanding of modern out-of-order superscalar processor architecture.
• Strong understanding the design and verification life cycle.
• Experience in CPU cache/memory subsystem verification is a plus
• Simulation and debugging with a Verilog based functional simulator.
• General functional verification experience with digital designs.
• Working experience in UNIX software environment.
• Strong problem-solving and debugging skills in both pre- and post-silicon environments.
• Exposure to leadership or mentorship is an asset.
• Familiarity with use of AI is a plus.

Academic Credentials

Bachelors or Master s degree in Electrical/Electronics Engineering, Computer Engineering, Computer Science or similar with a focus on computer architecture

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.