Associate III - VLSI

Role Description Debug and triage failures from simulation and emulation environments at core/subsystem level, covering:Frontend (Fetch/Decode)Execution & Load/StoreFloating PointCache hierarchyAnalyze and debug test cases written in assembly and C++-based verification environments.Develop and enhance automated debug and triage tools using scripting languages (Perl/Python/Ruby) and C++.Contribute to stimulus development:Directed and random test creationImprove regression efficiency and bug detectionWork on core debug infrastructure and improve debug turnaround time.Collaborate with cross-functional teams to identify coverage gaps, improve test quality, and address bug escape scenarios.Identify opportunities for automation and process improvements.Support post-silicon debug activities as needed.Explore and apply ML/AI-based techniques to improve debug and verification efficiency (good to have). Required Skills & Qualifications: 3-5 years of experience in ASIC/SoC Design Verification.Good understanding of:Computer Architecture (x86/ARM basics)Digital Design fundamentalsRTL conceptsFamiliarity with verification methodologies:C++/SystemVerilogUVM/OVM (preferred)Strong debugging and analytical skills.Exposure to simulation and/or emulation environments.Scripting knowledge (Python/Perl/Shell/Ruby) preferred. Preferred Qualifications: Exposure to processor subsystem verification (CPU core, caches, pipelines).Understanding of microarchitecture concepts (pipeline stages, memory hierarchy, execution units).Familiarity with assembly-level programming/debug.Awareness or exposure to ML/AI techniques in verification (nice to have). Soft Skills:Strong problem-solving mindset and attention to detail.Good communication and collaboration skills.Ability to work in a fast-paced, dynamic environment.Self-driven learner with a passion to explore and innovate.Team-oriented mindset ( We before Me ).

Skills vlsi design,uvm,computer architecture,digital design,c++,rtl,systemverilog,