Associate III - VLSI SD Char

Job Summary

Buffer Request Desired skills/knowledge: Experience and understanding of standard cell library design simulation. Understanding of concepts of balancing the cells, impact of width change on devices, issues in advanced technology nodes. Experience with at least one characterization tool (SiliconSmart/Liberate) for complete characterization of a library to generate the front end and back end views. Understanding of characterization methodologies for combinational, sequential cells and timing, power, capacitance models. Knowledge of Standard cell characterization and IO Characterization flows and methodologies, library verification and validation . Familiarity with circuit simulators, liberty syntax, library compiler, design compiler. Basic understanding of static timing analysis and synthesis. Scripting skills with perl, shell or python Setup simulation environment , write decks and perform design simulation. Write API/tcl coding for post processing liberty. Characterization and generation of front end and back end views for standard cell libraries Custom cell characterization setup and flows. Library verification and validation Apache(Redhawk) and voltus view generation and QA. Automation for the QA checks, for small tasks in setting up the flows for characterization and QA. Documentation of and recording the issues, debugs, solutions and new/enhanced work flows. Mentor and enhance the skill set of junior team members Exp: 3-7 years

Responsibilities

• Experience and understanding of standard cell library design simulation.
• Understanding of concepts of balancing the cells, impact of width change on devices, issues in advanced technology nodes.
• Experience with at least one characterization tool (SiliconSmart/Liberate) for complete characterization of a library to generate the front end and back end views.
• Understanding of characterization methodologies for combinational, sequential cells and timing, power, capacitance models.
• Knowledge of Standard cell characterization and IO Characterization flows and methodologies, library verification and validation.
• Familiarity with circuit simulators, liberty syntax, library compiler, design compiler.
• Basic understanding of static timing analysis and synthesis.
• Scripting skills with perl, shell or python.
• Setup simulation environment , write decks and perform design simulation.
• Write API/tcl coding for post processing liberty.
• Characterization and generation of front end and back end views for standard cell libraries.
• Custom cell characterization setup and flows.
• Library verification and validation Apache(Redhawk) and voltus view generation and QA.
• Automation for the QA checks, for small tasks in setting up the flows for characterization and QA.
• Documentation of and recording the issues, debugs, solutions and new/enhanced work flows.
• Mentor and enhance the skill set of junior team members.

Qualifications

• Exp: 3-7 years

Skills

• Standard cell library design simulation
• SiliconSmart
• Liberate
• liberty syntax
• library compiler
• design compiler
• static timing analysis
• scripting (perl, shell or python)
• API/tcl coding

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.