Associate III - VLSI PD SMG

Job Summary

Title: OS Engineer for PNR Methodology

Responsibilities

• Place-and-route (PD) Flow development and support
• Develop and support the execution of the full physical design flow, including Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), and Routing, DRC analysis, Timing functional ECO
• Automation Development: Develop and maintain automated design flows to reduce TAT (Turn-Around Time) and minimize manual errors.
• Custom Tooling: Utilize scripting languages (Tcl, Python, or Perl) to create custom scripts for data extraction, report parsing, and tool orchestration.
• Flow Optimization: Implement DOE (Design of Experiments) to determine optimal tool settings and repeater conditions for minimized clock latency and improved power.
• Root Cause Analysis: Debug complex timing violations, congestion issues, DRC electromigration (EM) failures etc
• Scripting: Advanced proficiency in Tcl (essential for Innovus) and Python/Perl

Qualifications

• Education: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 5-8 years
• Good to have: Worked on the flow development and support. Hands-on on the LEC, extraction, STA PV. Hands-on with Genus synthesis

Skills

• Innovus
• FC tools
• Tcl
• Python
• Perl
• Floorplanning
• Power Planning
• Placement
• Routing

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