Associate III - VLSI IOL

Requirements

• 4-8 years of hands-on experience in Analog, Mixed-Signal, and I/O Layout design.
• Strong exposure to advanced TSMC and Samsung technology nodes (2nm, 3nm, and 5nm).
• Proven experience in designing: High-Speed I/O (HSIO) General Purpose I/O (GPIO) DDR I/O (DDRIO).
• Strong knowledge of custom layout techniques, including device matching, common centroid, shielding, guard rings, and routing optimization.
• Experience with DRC, LVS, ERC, PEX, and layout closure.
• Hands-on experience with Cadence Virtuoso and industry-standard custom layout tools and flows.
• Good understanding of semiconductor manufacturing processes and physical design constraints.

Qualifications

• Preferred Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, VLSI, or a related field.
• Experience with successful tape-outs on advanced technology nodes.
• Strong analytical, debugging, and problem-solving skills.
• Excellent communication and collaboration skills.

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