Associate II - VLSI
UST Global · Hyderabad · onsite · Posted 44d ago
Undisclosed2–3 yrsfulltimeSourced from
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About this role
Job Summary
Engineering - Hardware Design Engineer 2 - Must have solid experience with memory technologies, and a desire to develop broader exposure to their downstream use in a dynamic, cutting edge VLSI synthesis environment. This role will provide key support for multiple projects in a globally distributed team.
Responsibilities
- Read and understand documentation of and answer end-user question regarding Synopsys memory compilers
- Generate compiled memory views and perform quality assurance on those views for each released version.
- Perform program management, tracking action items and progress against due dates.
Experience and Education
- Understanding of SRAMs and memory compilers (Synopsis Memory Compiler experience preferred) as well as VLSI design flow
- Familiarity with memory design and views of memories, e.g. Verilog, timing (.lib), LEF, GDS
- Familiarity with physical design verification, e.g. DRC and LVS
- Able to perform and interpret circuit simulations, e.g. using SPICE
- Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language
- 2-4 years of experience
- Release Comments: Skills:4 to 6 years experience
- Physical Design floor planning including power grid design
- Understanding of timing concepts and signoff
- Good hands-on experience in analyzing and fixing physical DRCs and analyzing LVS issues in Calibre tool
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Sourced from naukri
Skills
Program Managementunix shellVLSIphysical designlvsfloor planningsynthesiscompilershellDownstreamPerlVerilogVLSI DesignCompilerssynopsysUnixPythonQuality AssuranceHardware DesignGDSmemory technologies
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UST Global
IT Services & Consulting
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