Associate II - VLSI

Requirements

• 1-4 years of experience in ASIC/SoC Functional Verification.
• Strong proficiency in SystemVerilog and UVM.
• Good understanding of digital design fundamentals and verification methodologies.
• Experience with Verilog/SystemVerilog simulation and debugging.
• Knowledge of constrained-random verification and functional coverage.
• Familiarity with scripting languages such as Python, Perl, or Shell is an added advantage.
• Good debugging, analytical, and problem-solving skills.
• Excellent communication and teamwork skills.

Qualifications

• Preferred Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• Exposure to industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim.
• Knowledge of standard bus protocols such as AXI, AHB, APB, PCIe, USB, I2C, SPI, or UART is preferred.

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