ASIC RTL SoC Architect

The System On Chip (Soc) Architect role is a technical leadership role within AI Product Company Engineering team. This role is expected to have wide ranging contributions in:

Solutions engineering - define and develop solutions to customer mission needs using existing and new components

Product/SOC Architecture and Definition

SOC and IP microarchitecture

Specific Duties include:

• Meet with current and prospective customers to understand their mission goals and develop solutions.

• Develop architectural definition of upcoming products to include IP, Fabric and SOC architectures.

• Oversee definition, design, verification, and documentation for SoC development.

• Contribute to the micro-architectural features and specifications.

• Define module interfaces and formats for simulation.

• Perform RTL logic design and simulation for functional units, subsystems, and SoC full chip designs.

• Balance design trade-offs with modularity, scalability, DFX requirements, chassis compliance, power, area, and performance.

• Drive inter-organization collaboration, provide technical guidance, and mentor engineers.

• Utilize excellent written and verbal communications skills to collaborate internally across AI Product Company and with external customers.

Qualifications

Candidates must possess the minimum education requirements noted below and minimum required qualifications to be initially considered for this position.

Bachelor's degree in Electrical / Computer Engineering, Compute Science, or related field with 12+ years of relevant experience, or a Master's degree with 10+ years of relevant experience.

• Experience in computer architecture and experience in architectural specifications.

• Experience integrating components or IP blocks from internal and external providers.

• Experience in RTL/logic design on ASIC's, IP blocks or SOC's using System Verilog RTL coding.

Preferred Qualifications:

Experience interfacing with and supporting external customers.

Experience working with embedded products employing analog and/or RF IPs.

Experience in Platform Architecture.

Programming in C++, Perl and Assembly Algorithms.

Proprietary and 3rd-party RF logic design tools familiarity.