ASIC/RTL Design Engineer

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: ASIC/RTL Design Engineer
Experience: 8-10 Years

Location: BENGALURU

Full Time Employment

Role & responsibilities:

Description: SMTS SILICON DESIGN ENGINEER

THE ROLE:

Static Timing Analysis (STA) Lead with strong RTL collaboration and CDC sign-off ownership. The focus of this role will involve driving STA methodology and timing closure, collaborating with RTL and CDC teams to meet stringent power, performance, and area (PPA) targets on SerDes PHY IPs.

THE PERSON:
As a senior member of the SerDes IP Physical Design team, you will own STA of critical paths as primary discipline. Your focus will be ensuring timed paths are clean, understood, and communicated to the PD/RTL/Architecture team. Identify creative solutions for complex paths in multi-mode, functional, and test scenarios. This role requires deep technical expertise in physical design tools and methodologies and the ability to lead and mentor physical design engineers.

KEY RESPONSIBILITIES:

• Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively.
  • Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, at block and top-level, reviewing the timing arcs for the .lib generation.
  • GateCDC/GCA/TCM Analysis and create waivers or address design issues to reduce the waivers.
  • Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for test.
  • Evaluate the clock/reset-domain-crossing (CDC/RDC) issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible.
  • Drive CDC/RDC sign-off using tools such as Synopsys VC SpyGlass or Siemens 0in CDC tools
  • Review and validate RTL micro-architecture for timing impact and feedback to designers. Partner with RTL team on pipeline depth, retiming, and reset strategy to meet timing budgets
  • Identify opportunities to optimize clock skew and insertion delay across various corners and modes.
  • Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards.
  • Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations using AI toolset.
  

PREFERRED EXPERIENCE:

• Over 8-10+ years of professional experience in constraints generation, static timing analysis, RTL timing budgeting, and CDC/RDC sign-off, and IP-level timing and physical design, with a preference for high-performance SerDes designs.
  • Proven ability in converging timing driven RTL feedback/ECOs, and .lib arc generation.
  • Experience with STA closure on PHYs & understanding the timing requirements across digital and analog macro interfaces is a plus.
  • Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow.
  • Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks.
  • Excellent problem-solving, leadership, and communication skills and values team culture.
  • Capable of thriving in fast-paced environments and managing multiple projects simultaneously.
  

ACADEMIC CREDENTIALS:
• Masters degree in computer engineering/electrical engineering