ASIC Engineer (BB60FT RM 4357)

Position: ASIC Engineer (BB60FT RM 4357)

The role requires a strong ASIC engineer with deep hands-on experience in STA, synthesis, LEC, and timing constraints development. The candidate should be capable of writing and validating block-level and top-level constraints, performing sign off timing analysis using Tempus and PrimeTime, and driving closure across functional and DFT modes in an MMMC environment.
The engineer must also have experience in SDF generation and validation, GLS support, ETM/timing model generation, lint, CDC, and tape-out timing closure. The role involves close collaboration with RTL, design, SoC, physical design, DFT, and verification teams to resolve timing issues and ensure overall sign off readiness.

• Core domain: Static Timing Analysis, synthesis, and sign off support for ASIC design flows.
• Mandatory STA experience: Strong hands-on experience in both pre-layout and post-layout STA.
• Synthesis and LEC: Experience in synthesis flow execution and logic equivalence checking.
• Constraints development: Ability to write and implement block-level and top-level constraints for synthesis and timing analysis.
• Timing closure: Experience in MMMC timing closure across functional and DFT modes.
• Tool exposure: Hands-on usage of Tempus and PrimeTime for STA.
• GLS support: Experience in SDF generation, validation, and support to the functional verification team during GLS.
• ETM/timing models: Experience in ETM generation and validation at IP level.
• Cross-team collaboration: Worked closely with design, SoC, physical design, DFT, and verification teams.
• Sign off readiness: Support timing sign off and closure activities across multiple projects.
• Additional quality checks: Working knowledge of lint and CDC.
• Tape-out exposure: Experience supporting timing closure and tape-out on multiple projects.