ASIC Digital Engineer (SOC Validation)

As a SoC Validation/Verification Engineer, you will play a key role in ensuring the quality and reliability of our SoC designs. You will be responsible for:

• Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation.
• Independently developing and executing tests for verification and validation.
• Collaborating with cross-functional teams to drive closure of verification and validation activities.
• Signing off on verification and validation deliverables.
• Debugging and root cause analysis of issues found during validation.
• Developing and maintaining automated test environments and regression suites.
• Contributing to the continuous improvement of verification methodologies and best practices.

Your work will enable industry-leading data storage control SoCs that are deployed in high-volume consumer and enterprise products.

Why Join Us

At SanDisk, you ll be part of a team of highly skilled engineers solving complex verification challenges and driving innovation in data storage solutions. Your work will directly impact the performance and reliability of next-generation data solutions for both consumer and enterprise markets.

Together, we ll push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions. Qualifications

Qualifications:

Required:

• BE or MS degree in Electrical Engineering or Computer Engineering, with 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up.
• Deep understanding of C, embedded programming, and hardware/software co-validation methodologies.
• Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts.
• Proven history of developing and executing verification and validation strategies for complex SoCs.

Essential Duties and Responsibilities

• Ownership: End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure.
• Protocol Expertise: Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I C, I3C, SPI, AXI, AHB, and APB.
• Emulation Experience: Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage.
• Testbench Proficiency: Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components.
• Simulation Debug: Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis.
• Pre-/Post-Silicon Validation: Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases.
• Datapath Validation: Ability to understand and validate complex datapath flows of the controller, create datapath scenarios in SoC verification environments, and port them across pre-silicon and post-silicon environments.
• Post-Silicon Experience: Hands-on experience in post-silicon ASIC bring-up, validation, and debug.
• Firmware HAL Development: Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code to enable datapath, integration, and SoC-level validation and verification.
• Language Proficiency: Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development
• Validation Infrastructure: Build and maintain validation infrastructure, including test content, regression automation, and lab equipment integration (oscilloscopes, analyzers, logic probes).
• Debug Expertise: Proficiency in debugging SoC issues across multiple domains (digital logic, firmware, timing, low-power, DFT) using JTAG, trace, waveform capture, and performance counters.
• Power GLS Validation: Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns.
• Performance Stress Testing: Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios at the SoC level.
• Verification Methodology: Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification to ensure design quality and completeness.