ASIC Design Verification Engineer - Verilog/UVM
Pr Glolinks · Hyderabad · onsite · Posted 69d ago
Not disclosed3–10 yrsfulltimeSourced from
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About this role
ASIC Design Verification Engineer - Verilog/UVM
Sourced from hirist
Skills
VerilogUVMSystem VerilogASIC
About Pr Glolinks
Pr Glolinks
Management Consulting
51-200
employees
2002
24 years old
Chennai, Tamil Nadu
India
₹5.6L PA avg
Avg at Pr Glolinks
About
Provides consulting services aimed at transforming business processes and technologies for sustained excellence across diverse global markets.
Industries
Management Consulting
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10 reviews
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Culture
3.6
Career growth
3.5
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3.5
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