ASIC Design - Hardware Design Engineer

We are looking for experienced Hardware Design Engineers with hands-on ASIC design flow experience to help build and validate the next generation of flagship product.

This is a broad ASIC engineering role spanning frontend and backend design flows. Depending on your experience, you may be stronger in RTL design and verification OR synthesis and timing closure OR physical design and place-and-route, OR have experience working across multiple stages of the ASIC development flow.

You will work closely with our hardware, AI and software engineering teams to translate real-world ASIC design workflows into capabilities that can be supported, automated and validated within our flagship product.

What youll own

1. ASIC design flow expertise Bring practical knowledge of one or more stages of the ASIC development flow and help define how these workflows should be represented and supported within our flagship product.
2. Frontend design workflows Contribute expertise across RTL design, simulation, functional verification, linting, CDC analysis and synthesis, depending on your area of experience.
3. Backend implementation workflows Contribute expertise in areas such as place and route, physical design, static timing analysis, timing closure, power analysis and physical verification.
4. EDA tool integration and validation Work with commercial and other ASIC EDA tools to understand inputs, outputs, constraints, reports and failure modes, and help build reproducible workflows around them.
5. ASIC design automation Help identify opportunities to automate repetitive design and implementation tasks, while ensuring generated outputs can be validated using real industry-standard design tools.
6. Reference designs and test cases – Develop or contribute to representative ASIC designs, IP blocks, test cases and implementation flows that can be used to develop, test and benchmark Chipforge Studio.
7. Design constraints and diagnostics – Help define how design intent, constraints, tool outputs, warnings, errors and signoff information should be captured and interpreted by the platform.
8. End-to-end flow understanding – Work across the broader engineering team to ensure that decisions made at one stage of the ASIC flow are understood and handled correctly by downstream stages.
9. Documentation and engineering standards – Document workflows, assumptions, constraints, known limitations and validation criteria so that ASIC capabilities can be reproduced and scaled across the Chipforge platform.

Preferred candidate profile

1. Hands-on experience in one or more areas of the ASIC design flow, including RTL design, simulation, functional verification, synthesis, static timing analysis, place and route, physical design or timing closure.
2. Strong understanding of the overall ASIC design lifecycle and how frontend and backend stages interact.
3. Experience working with one or more commercial ASIC EDA environments from Cadence, Synopsys or Siemens, with practical exposure to the tools, flows and reports used during development.
4. Experience with additional ASIC design and verification tools, open-source flows or scripting environments is a strong advantage.
5. Frontend ASIC Design: Experience in one or more frontend ASIC design areas, including RTL design using Verilog/SystemVerilog, simulation, functional verification, linting, CDC analysis, synthesis and static timing analysis. Experience with verification methodologies such as UVM, assertions, coverage driven verification or formal verification is a strong advantage.
6. Backend ASIC Implementation: Experience in one or more backend ASIC implementation areas, including floorplanning, place and route, physical design, static timing analysis, timing closure, power analysis and physical verification.
7. Understanding of key ASIC design considerations such as clocking, reset, CDC, timing constraints, power, area, DFT and technology-dependent implementation requirements.
8. Ability to read and interpret tool reports, diagnose design or implementation failures, and understand how changes at one stage of the flow affect downstream results.
9. Comfort with scripting and automation using Python, Tcl, shell scripting or similar languages.
10. Experience working with modern engineering practices such as Git, CI/CD, automated testing, containerised environments and reproducible workflows is a strong advantage.
11. Clear technical communication skills and the ability to work closely with software and AI engineers who may not have deep ASIC implementation experience.

Nice to have

1. Experience taking one or more ASIC designs through a complete flow, from RTL through synthesis, implementation and signoff.
2. Experience with advanced verification methodologies, formal verification, emulation or FPGA prototyping.
3. Experience with physical verification, including DRC, LVS and signoff workflows.
4. Experience across both frontend and backend ASIC flows.
5. Experience developing or integrating EDA automation and custom design flows.
6. Exposure to open-source ASIC and EDA tools such as OpenROAD, OpenLane, Yosys, Verilator or related tools.
7. Experience with semiconductor IP, SoC integration, RISC-V, AI accelerators or other complex digital systems.
8. Exposure to AI/ML-assisted design workflows, code generation or automation of engineering workflows.

Company is building an AI-native semiconductor design platform that brings together hardware engineering, EDA, AI and software.

This role will work closely with hardware engineers, EDA specialists, AI engineers and platform engineers. The successful candidate should be comfortable operating in an environment where the workflows are still evolving and where practical engineering experience is essential to deciding what the platform should do.

We value engineers who understand real design flows, know where existing tools and processes break down, and can help turn that experience into robust, repeatable and scalable capabilities platform development.