ASIC Design Engineer | Simulation & Emulation , Test methodologies

Job Summary

Meet the Team:

Silicon one group delivers the silicon, optics, and hardware platforms for Ciscos core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world.

Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centres and across service provider, enterprise networks, and data centres with a fully unified routing and switching portfolio.

Come join us and take part in shaping Ciscos ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.

Your Impact

As a Design Verification Engineer specializing in Simulation Emulation, you will be responsible for developing and executing verification strategies to ensure the correctness and performance of complex hardware designs. Your primary focus will be on emulation platforms to accelerate verification cycles and improve coverage.

Key Responsibilities

• Develop and implement verification plans and test benches using emulation tools and methodologies.
• Collaborate with design and validation teams to identify verification requirements and coverage goals.
• Utilize emulation platforms to run large-scale verification tests and debug design issues.
• Analyse verification results, identify bugs, and work closely with design engineers to resolve issues.
• Maintain and enhance verification infrastructure and automation frameworks.
• Document verification processes, test cases, and results to ensure traceability and reproducibility.
• Stay current with emerging verification technologies and best practices, particularly in emulation.
• Mentor junior engineers and contribute to team knowledge sharing.

Minimum Qualifications

• Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
• Strong experience in Design verification methodologies using UVM or OVM
• Relevant experience in design verification with a strong emphasis Test Methodologies
• Exposure on Emulation Tools like Cadence Palladium, Synopsys Zebu etc
• Experience into Networking (Ethernet, AXI, AMBA, PCIe etc)
• Strong communication skills and ability to work as a team
• Post Silicon functional validation or debugging experience is a plus

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.