ASIC Design Engineer, High Speed IO

We are now looking for RTL Design Engineers for our High Speed IO IPs deployed in automotive chips. As one of the primary designers, you will be responsible for implementing USB, UFS, Ethernet or PCIe IPs for next-generation automotive chips. One should possess strong digital design and verification fundamentals.

What you'll be doing:

• As a designer, be responsible for making architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation.
• Own micro-architecture and RTL development of design modules.
• Micro-architect features to meet performance, power and area requirements.
• Work with HW architects to define critical features.
• Work with verification teams to verify the correctness of implemented features.
• Partner with timing, VLSI and physical design teams to ensure design meets timing, interface requirements and is routable.

What we need to see:

• BTech/MTech with 2+ years of experience in crafting complex units and CPU/micro-controller-based sub-systems.
• Knowledge of security standards, protocols and system security architectures of modern SoCs would be a significant plus.
• Excellent influencing skills resulting in collaboration with cross-cultural, multi-geography and matrixed teams.
• Good debugging, analytical and problem-solving skills.
• Great interpersonal skills and ability to work as an excellent teammate.