Analog Layout

Key Responsibilities
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Develop transistor-level and block-level Analog Mixed-Signal (AMS) layouts in SMOS10HV technology.
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Create and optimize floorplans considering performance, matching, area, routing, and reliability requirements.
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Translate sub-block schematics into physical layouts while maintaining the same hierarchy used in simulations.
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Implement layouts according to design documentation, layout guidelines, customer feedback, review comments, and back-annotation requirements.
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Ensure one-to-one correspondence between layout implementation and parameterized devices used in schematic simulations.
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Perform Design Rule Check (DRC) and resolve violations until achieving a clean signoff database.
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Perform Layout Versus Schematic (LVS) verification and resolve discrepancies until successful closure.
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Ensure compliance with all foundry-specific layout rules and process requirements.
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Generate extracted netlists and provide them to Design Engineers for post-layout simulation and back-annotation activities.
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Participate in layout reviews and implement corrective actions based on review findings.
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Maintain and update block review documentation with layout implementation details, observations, and recommendations.
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Work closely with circuit designers to optimize layout quality, performance, and manufacturability.
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Support tape-out activities and ensure timely delivery of layout milestones.
Required Qualifications
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Bachelor's or Master's degree in Electronics Engineering, VLSI, Microelectronics, or a related field.
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Hands-on experience in SMOS10HV process technology.
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Strong experience in Analog Mixed-Signal (AMS) Layout Design.
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Good understanding of:
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Analog layout methodologies
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Device matching techniques
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Symmetry requirements
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Common-centroid layouts
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Interdigitated structures
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Guard rings and shielding
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Experience performing:
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DRC
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LVS
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Parasitic Extraction (PEX)
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Layout signoff activities
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Ability to interpret schematics and convert them into optimized physical layouts.
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Strong understanding of hierarchy-based layout implementation.
Preferred Skills
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Experience in:
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High-voltage analog layouts
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Power Management ICs (PMIC)
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Automotive semiconductor products
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Mixed-signal IP development
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Knowledge of ESD and latch-up protection concepts.
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Understanding of post-layout simulation methodologies.
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Familiarity with reliability and manufacturability requirements.
EDA Tools
Experience with one or more of the following:
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Cadence Virtuoso
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Mentor Calibre (DRC/LVS/PEX)
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Cadence Pegasus
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Synopsys IC Validator
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Custom Compiler
Key Competencies
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Strong debugging and problem-solving skills.
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Attention to detail and layout quality.
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Effective communication and collaboration with design teams.
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Ability to work independently and manage complete layout ownership.
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Strong documentation and review skills.
Keywords
AMS Layout, Analog Layout, Mixed-Signal Layout, SMOS10HV, High Voltage Layout, Floorplanning, DRC, LVS, PEX, Layout Signoff, Cadence Virtuoso, Calibre, PMIC, Automotive Semiconductor.

Roles and Responsibilities
We are seeking a skilled AMS (Analog Mixed-Signal) Layout Engineer with hands-on experience in SMOS10HV technology. The candidate will be responsible for implementing high-quality analog and mixed-signal layouts from schematics, ensuring compliance with design specifications, foundry rules, and signoff requirements. The ideal candidate should possess strong expertise in floorplanning, layout execution, DRC/LVS closure, parasitic extraction, and post-layout support while collaborating closely with circuit design engineers throughout the development cycle.