Analog Layout Engineer

Role & responsibilities

• Experience in designing the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).
• Day-to-day tasks include floorplanning, device placement, routing of critical analog circuits, and optimization for noise, mismatch, parasitics, and area.
• The engineer will also run and analyze physical verification checks (DRC, LVS, ERC, and related signoff flows), debug issues, and maintain thorough documentation of layout revisions and methodologies.

Preferred candidate profile

• Strong expertise in Layout Design for analog and mixed-signal ICs, including device placement, routing, floorplanning, and layout optimization
• Hands-on experience with Physical Verification flows, including DRC, LVS, ERC, and familiarity with signoff methodologies.
• Proficiency with industry-standard EDA tools for analog layout and verification (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys tools or similar).
• Knowledge of CMOS process technologies, device physics fundamentals, matching techniques, and layout strategies for low-noise and high-precision circuits.
• Minimum 5+ years of relevant experience in analog layout engineering within the semiconductor or VLSI domain.
• Bachelors or Masters degree in Electronics, Electrical Engineering, VLSI, or a closely related discipline.

If interested, Please share your CV to [email removed] with Subject Line "Analog Layout_Years of Experience"