Analog Layout Engineer

Job Title: Analog Layout Engineer

Experience: 4 - 10 years

Role Summary

We are looking for an Analog Layout Engineer to deliver block-level custom and RF layouts on advanced FinFET nodes. The role spans floorplanning through tape-out, covering matching-critical device placement, physical verification, ESD and reliability closure, and close collaboration with circuit design teams on high-complexity analog and RF blocks.

Responsibilities

• Analog & RF Layout: Deliver block-level custom analog and RF layouts, applying matching, shielding, symmetry, and isolation techniques for high-complexity designs.
• Circuit Analysis: Analyze schematics and circuit intent with design engineers to translate performance requirements into layout constraints and floorplans.
• Floorplan to Tape-out: Own block floorplanning, device placement, and interconnect strategy from early planning through tape-out.
• Physical Verification: Run and close DRC, LVS, ERC, antenna, and DFM checks, and drive violations to clean sign-off.
• ESD & Latch-Up: Perform ESD verification and apply latch-up avoidance techniques including guard rings, well ties, and proper spacing.
• LDE & Reliability: Identify and fix LOD, WPE, and other layout-dependent effects, along with IR drop and electromigration issues, through placement and routing changes.
• Power Routing: Build robust power and ground distribution to meet IR and EM budgets without compromising area or matching.
• Collaboration & Debug: Collaborate with circuit design, ESD, and integration teams; debug layout and post-silicon issues and drive fixes to closure.
• Methodology: Adopt current industry layout methodologies and contribute to reusable templates, automation, and documentation.

Qualifications

• Education: Bachelor's or Master's degree in Electronics, Electrical, VLSI, or a related engineering field.

Required Skills

• Core Experience: 4 to 10 years of hands-on block-level analog layout experience, including custom and RF designs.
• Process Nodes: Hands-on experience on FinFET nodes, preferably 3nm to 7nm.
• Node Exposure: Experience with 8nm, 7nm, and 16nm.
• Layout Techniques: Strong knowledge of analog and RF layout techniques and current industry methodologies.
• Verification: Experience in circuit design analysis, layout implementation, LVS / DRC / ERC checks, and ESD verification for high-complexity RF designs.
• Project Cycles: Successfully completed at least two full project cycles from floorplan to tape-out.
• Reliability Effects: Good working knowledge of ESD, LOD, WPE, latch-up, IR drop, and EM issues and their fixes.

Preferred Skills

• Expertise in Cadence Virtuoso, Calibre, Assura, or PVS.
• Scripting in SKILL, Python, or Tcl for layout automation and checks.
• Exposure to high-speed SerDes, PLL, ADC / DAC, or PMIC block layouts.
• Experience with EM / IR analysis and reliability sign-off flows.