Analog Layout Engineer

Project Role :Analog Layout Engineer


Project Role Description :Design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Address parasitic effects, signal integrity, and power distribution to meet design specifications. Collaborate to ensure the layout meets functional, electrical, and manufacturing requirements.
Must have skills :Analog Layout

Good to have skills :NA
Minimum 7.5 year(s) of experience is required

Educational Qualification :15 years full time education

Summary:As an Analog Layout Engineer, you will design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Your typical day will involve addressing parasitic effects, signal integrity, and power distribution to meet design specifications. You will collaborate with various teams to ensure that the layout meets functional, electrical, and manufacturing requirements, contributing to the overall success of the projects you are involved in.

Roles & Responsibilities:

Expected to be an SME.

Collaborate and manage the team to perform.

Responsible for team decisions.

Engage with multiple teams and contribute on key decisions.

Provide solutions to problems for their immediate team and across multiple teams.

Mentor junior professionals to enhance their skills and knowledge in analog layout design.

Continuously evaluate and improve layout processes to enhance efficiency and effectiveness.

Professional & Technical Skills:Must Have Skills:Proficiency in Analog Layout.Working on layout design of owned blocks with Cadence Virtuoso XL. Working on block and top-level level layout verification with Calibre. Extensive PAD Ring and Top/Chip level layout experience Working with analog/mixed-signal and digital design teams to ensure proper layout design o Block level floor planning and layouto IC top level floor planning and area estimationo Using recommended layout and verification techniques, tools, and flows to produce optimal designso Generate post-layout extractiono Create layout related documentation and conduct layout reviewsPreferably experience in TSMC, Finfet, SERDES/ADC/DAC/PLL - good to have but not mandatory.

Strong understanding of layout design tools and methodologies.

Experience with parasitic extraction and signal integrity analysis.

Familiarity with manufacturing processes and design for manufacturability principles.

Ability to work collaboratively in a team environment and communicate effectively.

Additional Information:

The candidate should have minimum 7.5 years of experience in Analog Layout.

This position is based at our Bengaluru office.

A 15 years full time education is required.
Qualification15 years full time education