AMS Verification

Core Skills: Verilog-AMS | Real Number Modeling (RNM) | SystemVerilog | UVM | SPICE Debug

Key Responsibilities

• Behavioral Modeling: Design and verify block-level models using Verilog-A/AMS, SystemVerilog, or RNM for top-level mixed-signal simulations.
• Testbench & Simulation: Build UVM-based testbenches, automated checkers, and run SPICE + digital co-simulations for AMS IPs (ADCs, DACs, LDOs, PLLs, SerDes, GPIOs).
• Debug & Closure: Analyze waveform mismatches (WaveView, SimVision), debug interface/corner-case failures, and drive functional coverage closure alongside design teams.

Requirements

• Experience: 2+ years of hands-on experience in AMS/Mixed-Signal design verification and debug.
• Languages & Methodologies: Proficient in SystemVerilog, UVM, Verilog-AMS, and SVA.
• Tools Exposure: Familiarity with EDA tools such as Cadence Virtuoso, DiscoveryAMS, Xcelium, or Synopsys XA / PrimeSim.