AMS Verification engineer
Cyient · Hyderabad · onsite · Posted 54d ago
Undisclosed3–6 yrsfulltimeSourced from
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About this role
Required Skills & Qualifications
- Bachelor's/Master's degree in Electronics & Communication Engineering, Electrical Engineering, or related field.
- 3-5 years of experience in AMS Verification.
- Strong understanding of Analog Mixed-Signal design and verification concepts.
- Hands-on experience with:
- SystemVerilog
- UVM
- Verilog-AMS / Verilog-A
- Mixed-signal verification methodologies
- Experience with simulators such as:
- Cadence Xcelium
- Cadence AMS Designer
- Synopsys VCS AMS
- Siemens Questa ADMS
- Strong debugging and problem-solving skills.
- Experience in scripting using Python, Perl, Shell, or TCL.
- Good understanding of assertions, coverage concepts, and regression management.
Preferred Skills
- Experience in verifying high-speed interfaces, ADC/DACs, PLLs, SerDes, PMICs, or Sensor IPs.
- Familiarity with real-number modeling (RNM).
- Knowledge of AMS verification acceleration techniques.
- Experience with SoC-level integration and verification.
- Understanding of low-power verification concepts.
Roles and Responsibilities
Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.
Sourced from naukri
Skills
modelingScriptingBashSOCSensorverificationCadencephysical designtclAmsAnalogCircuit designingconceptsipPerlAdcASIC VerificationVerilogUVMSystem VerilogSOC VerificationVHDLRTL CodingRTL DesignSerdessynopsysdebuggingSynopsys VCSPythonDesign
About Cyient

Cyient
IT Services & Consulting
11.9k+
employees
1991
35 years old
Hyderabad/Secunderabad, Telangana
India
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Cyient delivers engineering solutions addressing digital and sustainable futures, serving a diverse client base while promoting cultural and environmental responsibility.
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