AMS Layout Engineer

• R1: Virtual
• R2: Virtual

• 7-9 yrs of hands-on experience in independence block/module layouts with Cadence Layout design tools
• Experience in TSMC 5nm or lower node is must.
• Well versed with layout design and verification tools - Cadence Virtuoso EXL/GXL, Calibre etc.
• Custom layouts for High-Speed Custom Analog/Digital blocks, such as Ring Oscillators, Dividers, Bias Blocks (Voltage & Current references), pre-drivers etc. in TSMC 3nm and below

• Custom layouts for High-Speed Custom Analog/Digital blocks, such as Ring Oscillators, Dividers, Bias Blocks (Voltage & Current references), pre-drivers etc. in TSMC 3nm and below,
• Independent in debugging and resolving the layout fixes in various verification flows
• Flexible to take different tasks in project.
• Have accountability and ownership on blocks & bigger macros assigned
• Responsible for running release flows and take to closure on time, adhering the milestones, raise concerns well in advance for any foreseen issues
• Communicate with the team on block level specs, to better integrate the top modules

• Completed layout designs, with desired quality, with all specified verification flows clean
• Create and check all relevant layout design views using sign-off tools and flows
• Documentation as per requirement.
• Desired Qualification : B.Tech/B.E./MS /M.E. /M tech in Electrical Engineering
• Desired Experience : 7-9 yrs of hands-on experience in block/module layouts with Cadence Layout design tools, exp in TSMC 5nm or lower node is must
• Well versed with layout design and verification tools - Cadence Virtuoso EXL/GXL, Calibre etc..
• Exp in leading module/macro level layout, communicating with various team members to better co-ordinate layout integrations
• Knowledge of scripting (SHELL, PERL, SKILL), excel is good to have.

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